In the prior art processors of different operational bit sizes (8, 16 or 32) are typically constructed of integrated circuits that have four input bits and four output bits. An example of such a four bit integrated circuit chip is the 2901 arithmetic chip which is used to implement an arithmetic logic unit in a processor. Also in a processor in a computer system, blocks of bytes as a page are assigned as required to store calculated results, and a multibyte calculation result may be stored between two blocks or pages. An invalid address occurs because a carry across a page-address boundary may cause data to reside in the subsequent block or page, but the carry may not be visible outside the ALU. This problem is particularly acute when addresses are being generated using inputs of a base address, an offset or displacement, and an operand length. Invalid or out-of-bound addresses may result with adverse effects.
Thus, there is a need in the art for an address boundary detector which can detect whether all bytes of a data item to be stored at a calculated address will fall within a block or page of memory.